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Silicon Designs - Key Facts
  • CSX700

    • 90nm
    • IBM 9SF High Performance Process
    • 250 Million Transistors
    • 17.4 x 17.4 sq mm die
    • 1152 FC-PBGA package

  • CSX600

    • 130nm
    • IBM 8SF High Performance Process
    • 128Million Transistors
    • 15.2 x 15.2 sq mm die
    • FC-BGA package

A CSX600 Wafer showing bare die with bumps attached ready for packaging.

Silicon Design


As the silicon process geometries have changed, so ClearSpeed’s proven expertise and delivery on advanced sub-micron silicon processes have been challenged and demonstrated time and time again.

ClearSpeed’s silicon design success can be attributed to:

ClearSpeed are working with foundry partners to evaluate sub-micron silicon technologies at 65nm, 45nm and 32nm.

EV7 routing map image
EV7 PE routing map
Click image to enlarge