Network on Chip

The need for computational performance simultaneously drives the need for bandwidth. Multi-core massively parallel processors need access to high bandwidth buses and memory subsystems.

ClearConnect overview
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A key element of ClearSpeed’s flexible approach to processor configuration is the ability to efficiently redesign, reconfigure and implement, correct by construction, high bandwidth networks on chip and also leverage the technology to further automate documentation, and generation of simulation models.

This concurrent approach to design automation maximizes the flow of data to and from the processing elements whilst minimizing the design risk in implementing a new processor configuration.

By extending the network to an external interface, the network can be extended beyond the boundaries of a device enabling multiple devices to be easily connected providing seamless scalability of the processing solution.