CSX700

The CSX700 architecture has been developed to address the requirements for accelerators in HPC and solve the Size, Weight and Power (SWAP) constraints which dominate high performance embedded applications.

By integrating processing, system interfaces and on-chip memory with ECC the CSX700 brings cost, reliability and performance advantages that solve leading edge, high performance embedded system requirements.

Low Power

Designed for low power consumption, the CSX700 combines aggressive clock gating techniques, custom silicon design with a low operating frequency. Simple clock management enables maximum application performance within defined power and thermal envelopes.

Performance

The MTAP processor is a massively data parallel architecture with a high degree of replication for efficiency and reliability. Performance is achieved from the high level of internal parallelism. The architecture is suited to sophisticated signal and image processing in the time and frequency domains.

Software Development

The CSX700 is supported by a professional software development kit based around an optimizing ANSI C compiler. This includes fully featured debug and profiling tools. In addition to the standard C libraries, a suite of optimized libraries that provide common functionality such as FFT, BLAS and LAPACK functions are available.

Performance

Features

  • Low power: 9W typical
  • High reliability RAS features: ECC on all on-chip memories
  • 96 GFLOPS, 32 & 64-bit IEEE 754 floating point
  • 48 GMAC/s integer performance
  • Eclipse-based SDK with integrated visual debugging and profiling
  • Simple programming model
  • Optimizing compiler for ANSI C with parallel programming extensions
  • CSX700 Processor Product Brief

    Architecture
    The CSX700 SoC design
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    Each PE contains:

    Architecture
    The MTAP processor core
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