CSX700
The CSX700 architecture has been developed to solve the Size, Weight and Power (SWAP) constraints which dominate high performance embedded applications.
By integrating processing, system interfaces and on-chip memory with error-correction the CSX700 brings cost, reliability and performance advantages that solve leading edge system requirements.
The MTAP processor coreClick image to enlarge
Low Power
Designed for low power consumption, the CSX700 combines aggressive clock gating techniques, custom silicon design with a low operating frequency. Simple clock management enables maximum application performance within defined power and thermal envelopes.
Performance
The MTAP processor is a massively data parallel architecture with a high degree of replication for efficiency and reliability. Performance is achieved from the high level of internal parallelism. The architecture is suited to sophisticated signal and image processing in the time and frequency domains.
Software Development
The CSX700 is supported by a professional software development kit based around an optimizing ANSI C compiler. This includes fully featured debug and profiling tools. In addition to the standard C libraries, a suite of optimized libraries that provide common functionality such as FFT, BLAS and LAPACK functions are available.
The CSX700 SoC designClick image to enlarge
Performance
- 250MHz core clock frequency
- 96 GFLOPS single or double precision
- 75 GFLOPS sustained double precision DGEMM
- 9W typical power dissipation
- 192 Gbytes/s internal memory bandwidth
- 2 x 4 Gbytes/s external memory bandwidth
- 4 Gbytes/s chip-to-chip bandwidth
Features
192 high-performance processing elements, each with:
- Dual 32 & 64-bit FPU
- 6 Kbytes high bandwidth memory
- PCIe x16 host interface
- 2 x 64-bit DDR2 DRAM interface with ECC support
- 256 Kbytes on-chip scratchpad memory
- On-chip instruction and data caches
- ECC protection on all on and off-chip memory
- ClearConnect NoC provides on-chip and inter-chip data network
- Host debug port
- 64-bit virtual, 48-bit physical addressing
- On-chip DMA controller