Intel Developer Forum, San Francisco – September 27, 2006 - ClearSpeed Technology (LSE: CSD), the only supplier of coprocessor acceleration technology exclusively focused on the high precision, high performance and low power requirements of the high performance and technical computing market, today announced its support for the Geneseo technology proposal to extend the PCI Express specification to address the needs of application acceleration.

Despite impressive advances in microprocessor technology such as the Dual-Core Intel® Xeon® Processor 5100 Series, a tradeoff still persists between designing a computer for the full range of applications and designing it for technical applications that make heavy use of floating-point arithmetic. The Geneseo proposal both endorses the role that acceleration technologies have to play and recognizes that there is a degree of processor to accelerator interaction that is inefficient under the current PCIe model.

“We’re always excited by improvements to the PCIe architecture to deliver better performance and functionality, but that’s not the main benefit here,” said Simon McIntosh-Smith, vice president of applications for ClearSpeed Technology. “The Geneseo proposal goes to the heart of the software programming model and has the potential to make accelerator technologies much more efficient and easier to use than they are with the current generation of PCIe.”

Both the current and next generation of PCI Express have been designed and optimized primarily for graphics and advanced I/O applications. The needs of application accelerators that complement general purpose processors by providing optimized processing for very specific applications and algorithms were not considered when the current specifications were agreed.

The Geneseo proposal is a set of extensions to PCIe hardware and software architecture intended to
improve platform performance in the application accelerator environment through four areas of enhancement:

• New semantics for reduced signaling and synchronization overhead
• Improving speed and efficiency of access to memory through new semantics and traffic management
• Transaction ordering attributes to optimize ordering in memory hierarchy
• Dynamic frequency or voltage-imposed performance and power operational modes

These enhancements will enable Geneseo accelerators to:
• use the existing PCIe architecture to initialize and manage devices,
• streamline application-to-accelerator interactions
• reduce system and software latency and overhead

“We have been very impressed with the approach to Geneseo,” said Ray McConnell, chief technology officer for ClearSpeed Technology. “Intel has played a leadership role in bringing the community together to collaborate on a process to deliver an open standard that will advance the adoption of acceleration technology benefiting users and vendors alike.”